This document is for Xen 3.0.0.(Some part of the document is for the later version.)

1 introduction

This document describes about xen/ia64 internals, especially on memory management and grant table. It is assumed that the readers have basic knowledge of IA64 address translation.
For example, translation registers, region registers and etc.

1.1 Related Documents

2 the IA64 architecture

This section describes IA64 key features which are important to understand Xen/IA64.
However virtual addressing is too basic so that it isn't being discussed here. For details, see the Intel IA64 architecture manual.

2.1 memory ordering

2.1.1 dependent load

The IA64 doesn't reorder memory access over dependent load unlike Alpha so that smp_read_barrier_depends() is defined as nop. But the Xen/IA64 doesn't exploit it (yet). Possibly there is a room for p2m conversion performance exploiting dependent read.

2.1.2 compiler barrier and volatile

According to C standard, “volatile” type qualifier requires compiler not-optimize. Moreover IA64 ABI defines that storing of volatile type must have release semantics(“.rel”) and loading must have acquire semantics(“.acq”).

2.1.3 atomic operation and memory barrier

Note that atomic operation doesn't mean memory barrier or ordered semantics. Especially simple atomic load/store has unordered semantics.

2.2 implemented address bits, region registers and psr.vm

unimplemented physical address bits

31 <= IMPL_PA_MSB <= 50
32 - 51 bit
NOTE: Xen/IA64 assumes that no real memory is assigned at the physical address
>= 2⁴⁰.

unimplemented virtual address bits

50 <= IMPL_VA_MSB <= 60
51 - 61 bit
When psr.vm = 1, it is decreased by 1.
PAL_VM_SUMMARY vm_info2.impl_va_msb
NOTE: IMPL_VA_MSB = 60 on Itanium2 and Xen/IA64 assumes IMPL_VA_MSB = 60

rid size

The number of bits implemented in the RR.rid field
18 - 24 bit depending on the processor implementation.
IA64_MIN_IMPL_RID_MSB = 17
PAL_VM_SUMMARY vm_info2.rid_size

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